8/4/2023 0 Comments Mosfet logic level![]() ![]() RFP2N10 2a, 80v And 100v, 1.05 Ohm, N-channel Power MOSFETs RFP2N08L 2a, 80v And 100v, 1.050 Ohm, Logic Level, N-channel Power MOSFETs RFP2N08 2a, 80v And 100v, 1.05 Ohm, N-channel Power MOSFETs RFP25N06 25a, 60v, 0.047 Ohms, N-channel Power MOSFETs Some Part number from the same manufacture Intersil Corporation NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE DRAIN TO SOURCE ON RESISTANCE vs DRAIN CURRENTįIGURE 6. ![]() FORWARD BIAS SAFE OPERATING AREAĠ.3 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VGS = 5V PULSE DURATION = 80µs DUTY CYCLE 0.5% MAX ON RESISTANCE 0.1 25oCįIGURE 5. NORMALIZED POWER DISSIPATION vs CASE TEMPERATUREįIGURE 2. = 25oC CURVES MUST BE DERATED LINEARLY WITH INCREASE IN TEMPERATUREįIGURE 1. SYMBOL VSD trr ISD = 7.5A ISD = 4A, dISD/dt = 100A/µs TEST CONDITIONS MIN TYP 225 MAX 1.4 UNITS V nsġ.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) ID MAX CONTINUOUS 10 Repititive rating: pulse width limited by maximum junction temperature. Pulsed: pulse duration = 300µs maximum, duty cycle 2%. PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. RDS(ON) V(plateau) td(ON) tr td(OFF) tf Qg(TOT) Qg(5) Qg(TH) RJC Gate to Source Leakage Current Drain to Source On Voltageĭrain to Source On Resistance (Note 2) Forward Transconductance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate Charge at 5V Threshold Gate Charge Thermal Resistance Junction to Case = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS = 1mA, VGS = 0V VGS = VDS, = 25oC, VDS = 65V, VGS = 125oC, VDS = 65V, VGS = 0V MIN 80 1 VGS = 0-10V VGS = 0-5V VGS = 0-1V VDD = 4.27 TYP MAX UNITS ns nC PARAMETER Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Tpkg 300 260 UNITS W/oCĬAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. TL Package Body for 10s, See Techbrief 334. TJ, TSTG Maximum Temperature for Soldering Leads 0.063in (1.6mm) from Case for 10s. IDM Maximum Power Dissipation.PD Derated above 25oC. VDGR Gate to Source Voltage.VGS Continuous Drain Current. RFP15N08L Drain to Source Breakdown Voltage (Note 1).VDS Drain to Gate Voltage (Note 1). 40 | Copyright © Intersil Corporation 1999Ībsolute Maximum Ratings = 25oC, Unless Otherwise Specified NOTE: When ordering, use the entire part number.ĬAUTION: These devices are sensitive to electrostatic discharge follow proper ESD Handling Procedures. Formerly developmental type TA09804.ġ5A, 80V rDS(ON) = 0.140 Design Optimized for 5 Volt Gate Drive Can be Driven Directly from Q-MOS, N-MOS, TTL Circuits SOA is Power Dissipation Limited 175oC Rated Junction Temperature Logic Level Gate High Input Impedance Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" This performance is accomplished through a special gate oxide design which provides full rated conduction at gate biases in the 3-5 volt range, thereby facilitating true on-off power control from logic circuit supply voltages. The is an N-Channel enhancement mode silicon gate power field effect transistor specifically designed for use with logic level (5 volt) driving sources in applications such as programmable controllers, automotive switching, and solenoid drivers. 80V, 0.140 Ohm, Logic Level, N-Channel Power MOSFET ![]()
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